1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular to testing of memory refresh operations.
2. Description of the Related Art
Memory devices are used in digital computer systems to store and retrieve electronic data at high speeds. Each item of data in memory, called a bit, is stored in a separate circuit or device known as a cell. Since computers use binary format to represent data, each cell can store one of two possible values (on or off). A typical memory system contains millions of bits organized as an array consisting of horizontal rows and vertical columns. Each cell shares electrical connections with the other cells in its row and column. The horizontal lines connected to all cells in a row are called word lines, and the vertical lines (along which data flows into and out of the cell) are called data or bit lines. Cells are therefore accessed by proper selection of the word and bit lines.
Several different types of memory are found in digital computers, one of which is dynamic random access memory (DRAM). Random-access memory is flexible in that it allows both the retrieval and storage of data to be performed quickly (as compared to Read-only Memory, or ROM). Dynamic RAM differs from static RAM (SRAM) in that it stores a value in a memory cell by either charging or discharging a capacitor. The cell retains its value only as long as the capacitor remains charged (typically a few milliseconds). Therefore, the capacitor in the cell needs to be periodically recharged, or refreshed. SRAMs, on the other hand, retain a value in a cell until either another value is stored or the power supply is interrupted.
DRAMs, while typically slower than SRAMs, are less expensive and are generally used to implement large arrays in a computer system, such as main memory. DRAMs are less expensive than SRAMs because their memory cells are designed to be as simple as possible. Sacrificing circuitry for compactness, though, results in a less robust output signal from the cell. Peripheral logic such as sense amplifiers, memory registers, and output drivers is needed to properly restore the electrical characteristics of the cell's output to be compatible with the rest of the system. Reliability is also an issue when dealing with a dynamically stored value. Although the refresh operation is designed to periodically recharge a cell's storage element, some memory cells in the array may be weak in the sense of holding charge. If the storage element in a cell discharges too quickly, it will result in a loss of that data bit.
One implementation of a compact DRAM design is the three-transistor memory cell (3T cell). The 3T cell includes a storage transistor, which maintains the value of the cell, a read transistor for retrieving the value of the cell, and a write transistor, for storing a value into the cell. One type of transistor that can be used in this cell is the Metal-Oxide-Silicon Field-Effect Transistor (MOSFET). A MOSFET has a gate terminal separated from a silicon substrate by a thin layer of insulating material. Furthermore, the MOSFET has a channel extending between two diffused regions in the substrate, called the source terminal and the drain terminal. The fourth terminal, the substrate, is typically held at a non-conducting voltage. The source and drain are electrically disconnected unless a voltage potential from the transistor's gate to its source (V.sub.GS) surpasses a threshold voltage (V.sub.T) characteristic of the transistor. In this case, current begins to flow between the source and drain. When V.sub.GS is less than V.sub.T, the current flowing in the channel (known as the subthreshold leakage current) is considerably smaller than when V.sub.GS is greater than V.sub.T.
To understand the causes of subthreshold leakage current, the structure and operation of a MOSFET must be considered. The source and drain terminals of the transistor each form a reverse-biased junction with the substrate. At values of V.sub.GS below V.sub.T, these terminals are electrically disconnected from one another. At each of these junctions, one side of the junction has more positive charge carriers, and the other has more negative carriers. This heavy concentration of charge carriers is called doping. (In an n-channel transistor, the source and drain are negatively doped, and the substrate is positively doped). When these two regions come into contact, the differing charge concentrations cause a flow of negative carriers to the positively-charged region and a flow of positive carriers to negatively-charge region. As the carriers move about, an electric field is built up between the two regions. Eventually, an equilibrium is reached in which the electric field exactly balances the tendency of the charge carriers to migrate. A potential barrier is thus erected between the two types of materials that prevents current from flowing. Furthermore, a region is built up at the junction that is almost entirely devoid of any charge carriers. This area is known as the depletion region.
In large geometry MOSFETs, the potential barrier across the depletion region is great enough to restrict most leakage current. The electric fields created by the source-substrate junction and the drain-substrate junction are far enough part so that one field does not sufficiently lower the barrier enough to produce current injection. This is true even as drain voltage (V.sub.D) is increased, for in long-channel devices, the leakage current is substantially independent of the drain-source voltage V.sub.DS.
In short-channel transistors, however, an effect called drain-induced barrier lowering (DIBL) becomes important. DIBL results when the drain is sufficiently close to the source, such that the electric field caused by the drain-substrate junction lowers the source barrier enough so that current will flow. There are two components to DIBL. First, even if V.sub.DS is zero, the channel might be short enough such that there is overlap between the depletion regions of the drain and source terminals. This effect by itself may be enough to induce current flow. Secondly, as V.sub.DS is increased, the electric field of the drain junction may extend into the source region, again lowering the potential barrier. The subthreshold leakage current also has an exponential dependence on V.sub.G (and hence, V.sub.GS). As V.sub.GS increases, attracting more charge carriers to the channel, more current will flow.
In large geometry MOSFETs (channel lengths greater than one micron, the subthreshold leakage current is usually small enough to be ignored. For short-channel devices, however, this current flow may, in many instances, be significant. In the 3T cell, in which the write transistor is connected to the gate of the storage transistor, the subthreshold leakage current through the write transistor is a primary factor in the rate of discharge of the storage transistor. The greater the leakage current, the faster the cell discharges.
To prevent discharging to a degraded voltage level, the refresh operation is performed on each cell in a memory array at a fixed interval. The time between successive refresh operations is called the refresh interval, and is selected based on physical characteristics of the cell's transistors. The integrity of data in a memory system depends on each cell being able to hold its logic state throughout the duration of the refresh interval.
During manufacture of memory arrays, a test is conducted to insure that each cell meets the specification for the refresh interval. If this test is not performed with a comparatively large subthreshold leakage current, the memory cell could still be susceptible to failure under worst-case leakage conditions. To improve test coverage, it would therefore be desirable to increase the subthreshold leakage current during the refresh interval test of the 3T cell.